FMGALS Workshop at the 12th International FME Symposium

 

FORMAL METHODS FOR GLOBALLY ASYNCHRONOUS LOCALLY SYNCHRONOUS (GALS) ARCHITECTURE

 
 

(FMGALS 2003)

 

  
 

In conjunction with the 12th International FORMAL METHODS EUROPE SYMPOSIUM

  
 

&

  
 

In cooperation with ACM SIGDA and ACM SIGARCH

 

  
 

Date: September 13, 2003 

  

 

 

Overview

Relevance to FM Community

Program Committee

Important Dates

Venue

Registration - NEW

Logistics

Program - NEW

 

Please Note! The Deadline for paper submission has been extended.
The New Deadline is June 22nd, 2003.

 

Overview of the Workshop

As chips grow in speed and complexity, global control of an entire chip using a single clock is becoming increasingly challenging.  In the future, large-scale systems-on-a-chip (SoC's) are therefore likely to be composed of several timing domains.  Each such domain could be either clockless (i.e.,asynchronous), or controlled by its own local clock.

Globally Asynchronous Locally Synchronous (GALS) architecture is emerging as the architecture of choice for future SoC's with multiple timing domains. In GALS systems, each timing domain is locally clocked, and asynchronous communication schemes are used to glue all of the domains together.  Thus, unlike purely asynchronous design, GALS design is able to make use of the significant industrial investment in synchronous design tools.

There is an urgent need for formal methods for GALS systems.  In synchronous designs, formal methods and design automation have played an enabling role in the continuing quest for chips with every greater complexity.  Due to the inherent subtleties of asynchronous circuit design, formal methods are likely to be vital to the success of the GALS paradigm.  This workshop aims at bringing together researchers from different communities interested in GALS design, and in applying formal methods in creating CAD tools enabling correct by construction GALS design.

FMGALS-03 invites papers on formal methods for GALS systems.  However, since this is the first FMGALS workshop, we also invite formal methods that target any type of architecture that combines synchronous and asynchronous notions of timing.  Submissions reporting preliminary work are also encouraged.  In particular, contributions are invited on the following topics, but not limited to:

-   formal design and synthesis techniques for GALS 

     systems

-   formal verification of GALS systems

-   formal methods for analysis of GALS systems

-   hardware compilation of GALS systems

-   latency-insensitive synchronous systems

-   mixed synchronous-asynchronous systems

-   synchronous/asynchronous interaction at different

    architectural levels

-   clocking, interconnect and interface issues in deep- 

    submicron design

-   polychronous, pausable clock, source synchronous, and

    pleisochronous systems

-   modeling of interfaces between multiple timing

    domains

-   system decomposition into GALS architectures

-   formal aspects of system-on-chip (SoC) and network-

     on-chip (NoC) design 

-   tool papers
-   motivating case studies, comparisons, and applications


We will publish an edited volume based on selected workshop papers after the
workshop.  Informal workshop notes will be available at the workshop for the
benefit of the attendees.
 

Please submit a manuscript of no more than 10 pages in the LNCS format by June 15, 2003 to one of the following email addresses:

shukla@vt.edu

jean-pierre.talpin@irisa.fr